发明名称 Decoder parameter estimation using multiple memory reads
摘要 An apparatus including a memory array and control circuitry. The control circuitry is configured to, based at least on a plurality of read comparison results, determine a number of memory cells of the memory array that have threshold voltages that fall into each of a plurality of voltage ranges. The control circuitry is further configured to, based at least on the number of memory cells that have threshold voltages in each of the plurality of voltage ranges, estimate an offset amount that a center voltage between two threshold voltage distributions differs from a center reference voltage. The control circuitry is further configured to read one or more of the plurality of memory cells based at least in part on the estimated offset amount.
申请公布号 US8576625(B1) 申请公布日期 2013.11.05
申请号 US201113089135 申请日期 2011.04.18
申请人 YANG XUESHI;CHILAPPAGARI SHASHI KIRAN;MARVELL INTERNATIONAL LTD. 发明人 YANG XUESHI;CHILAPPAGARI SHASHI KIRAN
分类号 G11C16/06 主分类号 G11C16/06
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