发明名称 |
Delay test device and system-on-chip having the same |
摘要 |
A test device for a system-on-chip includes a sequential logic circuit and a test circuit. The sequential logic circuit generates a test input signal by converting a serial input signal into a parallel format in response to a serial clock signal and a serial enable signal and generates a serial output signal by converting a test output signal into a serial format in response to the serial clock signal and the serial enable signal. The test circuit includes at least one delay unit that is separated from a logic circuit performing original functions of the system-on-chip, performs a delay test on the at least one delay unit using the test input signal in response to a system clock signal and a test enable signal, and provides the test output signal to the sequential logic circuit, where the test output signal representing a result of the delay test.
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申请公布号 |
US8578227(B2) |
申请公布日期 |
2013.11.05 |
申请号 |
US20100944787 |
申请日期 |
2010.11.12 |
申请人 |
SON YOUNG-JAE;YOON YONG-JIN;CHO UK-RAE;SAMSUNG ELECTRONICS CO., LTD. |
发明人 |
SON YOUNG-JAE;YOON YONG-JIN;CHO UK-RAE |
分类号 |
G01R31/28 |
主分类号 |
G01R31/28 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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