| 摘要 |
A signal processing device to utilize multiple channel phase detection includes a first phase detector for a first Phase Locked Loop (PLL) of a first channel, the first phase detector to generate phase error information from an input of the first channel. The device also includes a second phase detector of a second PLL of a second channel, the second phase detector to generate phase error information from an input of the second channel. Both the first PLL and the second PLL are to receive phase error information from both the first phase detector and the second phase detector. |
