发明名称 Method of manufacturing semiconductor integrated circuit device
摘要 In the present invention, in the exposure to light of a memory cell array or the like of a semiconductor memory or the like, when a group of unit openings for etching the STI trench regions in which the unit openings for etching the STI trench regions each having a rectangular shape are arranged in rows and columns are transferred by the exposure onto a negative resist film, multiple exposure is appropriately used which includes a first exposure step using a first optical mask having a group of first linear openings extending in a column direction and a second exposure step using a second optical mask having a group of second linear openings extending in a row direction.
申请公布号 US8569144(B2) 申请公布日期 2013.10.29
申请号 US201213365183 申请日期 2012.02.02
申请人 FUNAYAMA KOTA;CHAKIHARA HIRAKU;RENESAS ELECTRONICS CORPORATION 发明人 FUNAYAMA KOTA;CHAKIHARA HIRAKU
分类号 H01L21/76;G03C5/18 主分类号 H01L21/76
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