| 摘要 |
A method for testing an integrated circuit, the method including performing a series of at least three tests, each including: selecting two nodes among at least three nodes for taking a clock signal from an integrated circuit, taking two clock signals at the two selected taking nodes during a test duration, detecting and counting events appearing in a jitter signal between the two clock signals taken, during the test duration, and determining from numbers of events counted a test result proportional to a sum of jitter variances of the two clock signals taken, and at the end of the series of tests, determining by a matrix calculation the jitter variance of each clock signal taken.
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