发明名称 |
SOFT ERASE OPERATION FOR 3D NON-VOLATILE MEMORY WITH SELECTIVE INHIBITING OF PASSED BITS |
摘要 |
<p>An erase operation for a 3D stacked memory device selectively inhibits subsets of memory cells which meet a verify condition as the erase operation progresses. As a result, the faster-erasing memory cells are less likely to be over-erased and degradation is reduced. Each subset of memory cells can be independently erased by controlling a select gate, drain (SGD) transistor line, a bit line or a word line, according to the type of subset. For a SGD line subset or a bit line subset, the SGD line or bit line, respectively, is set at a level which inhibits erase. For a word line subset, the word line voltage is floated to inhibit erase. An inhibit or uninhibit status can be maintained for each subset, and each type of subset can have a different maximum allowable number of fail bits.</p> |
申请公布号 |
WO2013158556(A1) |
申请公布日期 |
2013.10.24 |
申请号 |
WO2013US36615 |
申请日期 |
2013.04.15 |
申请人 |
SANDISK TECHNOLOGIES, INC.;COSTA, XIYING;LI, HAIBO;HIGASHITANI, MASAAKI;MUI, MAN, L. |
发明人 |
COSTA, XIYING;LI, HAIBO;HIGASHITANI, MASAAKI;MUI, MAN, L. |
分类号 |
G11C16/16;G11C5/02;G11C16/04;G11C16/34;H01L27/115 |
主分类号 |
G11C16/16 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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