发明名称 |
System having improved surface planarity for bit material deposition |
摘要 |
The present invention provides a method of fabricating a portion of a memory cell, the method comprising providing a first conductor in a trench which is provided in an insulating layer and flattening an upper surface of the insulating layer and the first conductor, forming a material layer over the flattened upper surface of the insulating layer and the first conductor and flattening an upper portion of the material layer while leaving intact a lower portion of the material layer over the insulating layer and the first conductor.
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申请公布号 |
US8565016(B2) |
申请公布日期 |
2013.10.22 |
申请号 |
US20080153073 |
申请日期 |
2008.05.13 |
申请人 |
YATES DONALD L.;DREWES JOEL A.;MICRON TECHNOLOGY, INC. |
发明人 |
YATES DONALD L.;DREWES JOEL A. |
分类号 |
G11C11/14;H01L21/3205;G11C11/00;G11C11/15;H01L21/768;H01L21/8246;H01L27/105;H01L27/22;H01L43/08 |
主分类号 |
G11C11/14 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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