发明名称 |
RC Corner Solutions for Double Patterning Technology |
摘要 |
A method includes determining model parameters for forming an integrated circuit, and generating a techfile using the model parameters. The techfile includes at least two of a C_worst table, a C_best table, and a C_nominal table. The C_worst table stores greatest parasitic capacitances between layout patterns of the integrated circuit when lithography masks comprising the layout patterns shift relative to each other. The C_best table stores smallest parasitic capacitances between the layout patterns when the lithography masks shift relative to each other. The C_nominal table stores nominal parasitic capacitances between the layout patterns when the lithography masks do not shift relative to each other. The techfile is embodied on a tangible non-transitory storage medium.
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申请公布号 |
US2013275927(A1) |
申请公布日期 |
2013.10.17 |
申请号 |
US201213479076 |
申请日期 |
2012.05.23 |
申请人 |
SU KE-YING;CHAO HSIAO-SHU;CHENG YI-KAN;TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD. |
发明人 |
SU KE-YING;CHAO HSIAO-SHU;CHENG YI-KAN |
分类号 |
G06F17/50 |
主分类号 |
G06F17/50 |
代理机构 |
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主权项 |
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