Integrated circuit design using through silicon vias

摘要

A method of integrated circuit design using through silicon vias (TSVs) can include determining that a stress field to which a first active circuit element of a circuit block is exposed and a stress field to which a second active circuit element of the circuit block is exposed are mismatched. Mismatch between the stress field of the first active circuit element and the stress field of the second active circuit element can be reduced by modifying a layout of the die for a TSV.