| 摘要 |
PURPOSE: A clock delay domino logic circuit and devices including the same are provided for on-chip variation (OCV). CONSTITUTION: A clock delay doming logic circuit (10A) comprises precharge circuits (P11-P1n), evaluation circuits (N11-N1n), logic networks (11-1-11-n), and phase controlling circuits (13-1A-13-nA). The precharge circuit controls the connection between a first node and a dynamic node by responding to a clock signal. The evaluation circuit controls the connection between a second node and an evaluation node by responding to the clock signal. The logic network is connected between a dynamic node and the evaluation node and determines the logic level of the dynamic node based on multiple input signals. The phase controlling circuit outputs the logic level of the evaluation circuit or outputs the logic level of the first node according to the level of the clock signal. |
