| 摘要 |
PURPOSE: A reduced pin count (RPC) memory bus interface device including a read data strobe signal using a variable latency technique and a method thereof provides the balance between the bus performance and the required number of bus signals. CONSTITUTION: A chip selector (215) delivers a chip select signal indicating the time when a peripheral device is activated. A memory bus interface supports communications between a host device and a peripheral device. A differential clock pair (220) delivers a differential clock signal including a first and a second differential clock signals. A read data strobe (230) delivers a read data strobe signal from the peripheral device. A data bus (235) delivers commands, addresses, and data information. The differential clock pair and the read data strobe transmit data in a dual data rate (DDR) mode. [Reference numerals] (210) RPC bus interface |
