发明名称
摘要 <p>When picture data is stored in memory units 0 through 3 and image decoding units 0 through 3 decode the data in parallel, a picture having macroblock lines 0 through 134 is divided into four areas and stored in the memory units 0 through 3. The area in a picture assigned to each image decoding unit is fixed by allowing the image decoding unit 0 to constantly take charge of the macroblock lines 0 through 3 of each picture. The image decoding unit for taking charge of the process of an area at a lower portion of a picture shifts the process timing on the same picture so that the same assigned area of the picture can be processed after the completion of the process of another image decoding unit taking charge of the area above the area assigned to the image decoding unit taking charge of the lower area.</p>
申请公布号 JP5309700(B2) 申请公布日期 2013.10.09
申请号 JP20080146185 申请日期 2008.06.03
申请人 发明人
分类号 H04N19/00;H04N19/42;H04N19/423;H04N19/436;H04N19/503;H04N19/593;H04N19/60;H04N19/61;H04N19/91 主分类号 H04N19/00
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