| 摘要 |
A single-ended read random access memory including a plurality of memory units, a clock generator, a bit line load circuit, a control processing unit, and a sensing unit is revealed. The memory units are coupled to a bit line and the clock generator is for generating a clock signal. The bit line load circuit charges the memory units to an operating voltage according to the clock signal. The control processing unit controls at least one of the memory units according to the clock signal to make the memory unit store a stored voltage according to the operating voltage. The sensing unit generates a sensing threshold according to the clock signal and a data dependency, and outputs a data signal according to the sensing threshold and the stored voltage. The operating voltage includes a noise whose ratio to the operating voltage is inversely proportional to the operating voltage. |
