TIMING OPTIMIZATION FOR MEMORY DEVICES EMPLOYING ERROR DETECTION CODED TRANSACTIONS

摘要

Systems, methods, and apparatuses are directed to optimizing turnaround timing of successive transactions between a host and a memory device. The host includes framing logic that generates a write frame that includes a plurality of data bits and an error bit checksum that is appended at the end of the data bits. The host further includes a bus infrastructure configured to accommodate the transfer of the write frame to the memory device and logic that defines the turnaround time to begin at a time instant that immediately follows the transfer of the data bits of the write frame. The turnaround time measures the time delay at which a succeeding write frame is to be transferred. In this manner, the turnaround time is optimized to enable the earlier initiation of successive data operations, thereby reducing the overall latency of successive back-to-back transactions.