| 摘要 |
A system for intracell interference suppression having a feedback loop, the feedback loop comprising: an interference suppression module (102) comprising an inter-cell interference suppression module (104) to suppress inter-cell interference, the interference suppression module further comprising an intra-cell interference suppression module (106) to suppress intra-cell interference; a pre-equalization module (108) coupled to an output of the interference suppression module (102); a chip equalization weight calculation module (116) coupled to an output of the pre-EQ module; a delay match module (114) coupled to the output of the pre-equalization module (108); a chip-level equalization module (118) coupled to an output of the chip-equalization weight calculation module (116), the chip-equalization module (118) further being coupled to an output of the delay match module (114); a downlink shared channel, DSCH, despreader (120) coupled to an output of the chip-level equalization module (118); a shared control channel, SCCH, despreader (122) coupled to an output of the chip-level equalization module (118); and a high-speed shared control channel, HS-SCCH, decoding module (124) coupled to an output of the shared control channel, SCCH, despreader (122) wherein an output of the HS-SCCH decoding module is coupled to the DSCH module, wherein the output of the high-speed shared control channel, HS-SCCH is further coupled to the intra-cell interference suppression module (106). |
