| 摘要 |
The pulse generation circuit generates a first pulse signal and a complementary second pulse signal. The first and second pulse signals are activated simultaneously in a normal mode and activated selectively in response to a test input signal in a test mode. A multiplexing input circuit selects and outputs one of a data input signal and a test input signal as a latch input signal in response to the first pulse signal and the second pulse signal. The latch input signal corresponds to the data input signal in the normal mode and corresponds to the test input signal in the test mode. The latching circuit latches the latch input signal to generate data output signal. The length of data transfer path is reduced, and DtoQ delay can be decreased. |
