发明名称 |
Methods and apparatus for efficient modification of values within computing registers |
摘要 |
In some embodiments, an apparatus includes a register having a first portion and a second portion. The first portion of the register has multiple bits and the second portion of the register has multiple bits. Each bit from the multiple bits of the first portion of the register is associated with a bit from the multiple bits of the second portion of the register such that a bit from the multiple bits of the first portion of the register is set for its associated bit from the multiple bits of the second portion of the register to be written.
|
申请公布号 |
US8549251(B1) |
申请公布日期 |
2013.10.01 |
申请号 |
US20100968884 |
申请日期 |
2010.12.15 |
申请人 |
VEMULA MURALI;SHENOY SATHISH;JUNIPER NETWORKS, INC. |
发明人 |
VEMULA MURALI;SHENOY SATHISH |
分类号 |
G06F13/00;G06F13/28 |
主分类号 |
G06F13/00 |
代理机构 |
|
代理人 |
|
主权项 |
|
地址 |
|