发明名称 Tightly coupled scalar and boolean processor with result vector subunit controlled by instruction flow
摘要 Methods and apparatus relating to a tightly coupled scalar and Boolean processor are described. In an embodiment, a Boolean unit may include a result vector subunit. The result vector subunit may be controlled by an instruction flow that is managed by a scalar unit. Other embodiments are also disclosed.
申请公布号 US8549256(B2) 申请公布日期 2013.10.01
申请号 US20070623297 申请日期 2007.01.15
申请人 NARAD CHARLES;INTEL CORPORATION 发明人 NARAD CHARLES
分类号 G06F13/00;H04L12/24;H04L12/56;H04L29/06 主分类号 G06F13/00
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