发明名称 Clock-free activation circuit
摘要 A circuit for recovering data from an incoming data stream according to one embodiment includes a capacitor and a substantially constant current source for charging the capacitor. A subcircuit generates a signal causing the capacitor to discharge upon detecting a first type of transition in the incoming data stream, the capacitor re-charging upon being at least partially discharged. A comparator compares a voltage on a node coupled to the capacitor to a reference voltage, the comparator outputting a first signal if the voltage on the node is higher than the reference voltage and outputting a second signal if the voltage on the node is lower than the reference voltage, the first signal being associated with a first logic value, the second signal being associated with a second logic value.
申请公布号 US8548098(B2) 申请公布日期 2013.10.01
申请号 US20050305648 申请日期 2005.12.15
申请人 SHYU JYN-BANG;OLAH ROBERT;MITTAL ROHIT;INTELLEFLEX CORPORATION 发明人 SHYU JYN-BANG;OLAH ROBERT;MITTAL ROHIT
分类号 H04L27/00;H03D3/22 主分类号 H04L27/00
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