发明名称 CLOCK SUPPLY CIRCUIT
摘要 PROBLEM TO BE SOLVED: To provide a circuit for supplying a clock signal to a load having a clock input section which suppresses power consumption.SOLUTION: A clock generation section 11 generates a clock signal 13 having an amplitude corresponding to an absolute value of a potential difference between a lower limit value of a high level input voltage Vand an upper limit value of a low level input voltage Vfor a load 20 having a clock input section 21. A level shift section 12 causes a potential shift while maintaining the amplitude of the clock signal 13 such that a high level potential of the clock signal 13 is not less than the lower limit value of the high level input voltage Vand that a low level potential of the clock signal 13 is not more than the upper limit value of the low level input voltage V. A clock signal 14 with the potentials thus shifted by the level shift section 12 is supplied to the clock input section 21.
申请公布号 JP2013187602(A) 申请公布日期 2013.09.19
申请号 JP20120049050 申请日期 2012.03.06
申请人 NIPPON KODEN CORP 发明人 SUZUKI TETSUO
分类号 H03K19/0175 主分类号 H03K19/0175
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