发明名称 VOLTAGE MARGIN BASED BAUD RATE TIMING RECOVERY IN A COMMUNICATION SYSTEM
摘要 Described embodiments provide a method of recovering timing data from a received signal. An analog-to-digital converter (ADC) of a receiver generates an actual ADC value for each bit sample of a received signal. Each bit sample occurs at an associated sample phase of the receiver. A margin phase detector of the receiver recovers timing information from the received signal by determining a target voltage margin value. The margin phase detector selects a window of n received bit samples, where n is a positive integer, and determines a voltage of a cursor bit of the selected window of bit samples. The margin phase detector determines, based on the target voltage margin value and the voltage of the cursor bit, whether the sample phase is correct. If the sample phase is incorrect, the margin phase detector adjusts the sample phase of the receiver by a predetermined amount.
申请公布号 US2013243056(A1) 申请公布日期 2013.09.19
申请号 US201213422226 申请日期 2012.03.16
申请人 CHMELAR ERIK V.;ITO CHOSHU;LSI CORPORATION 发明人 CHMELAR ERIK V.;ITO CHOSHU
分类号 H04B1/06;H04B1/02;H04B17/00 主分类号 H04B1/06
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