发明名称 Increased instruction issue rate and latency reduction for out-of-order processing by instruction chaining and collision avoidance
摘要 A technique for operating a processor includes storing a first result to a writeback buffer, in response to a first execution unit of the processor attempting to write the first result of a first completed instruction to a register file of the processor at a same processor time as a second execution unit of the processor is attempting to write a second result of a second completed instruction to the register file. The writeback buffer is positioned in a dataflow between the first execution unit and the register file. A buffer full indicator logic is used to detect that the writeback buffer is unavailable. A buffer unavailable signal is transmitted, from the buffer full indicator logic, in response to detecting the writeback buffer is unavailable. In response to receiving the buffer unavailable signal, a buffer retrieving logic writes the first result from the writeback buffer to the register file.
申请公布号 GB201313825(D0) 申请公布日期 2013.09.18
申请号 GB20130013825 申请日期 2013.08.02
申请人 INTERNATIONAL BUSINESS MACHINES CORPORATION 发明人
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