发明名称 METHOD FOR DESIGNING SEMICONDUCTOR INTEGRATED CIRCUIT
摘要 PROBLEM TO BE SOLVED: To reduce a design time.SOLUTION: A method for designing a semiconductor integrated circuit includes the steps for: creating wiring in a first block having plural cells; if a wiring congestion area exists on a path for connecting between cells C1 and C2 included in the first block, acquiring wiring congestion information on a second block adjacent to the first block; and on the basis of the wiring congestion information, creating wiring for connecting between the cells C1 and C2 by way of the second block.
申请公布号 JP2013182472(A) 申请公布日期 2013.09.12
申请号 JP20120046628 申请日期 2012.03.02
申请人 TOSHIBA CORP 发明人 YAMAOKA HIROAKI
分类号 G06F17/50;H01L21/82 主分类号 G06F17/50
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