| 摘要 |
One aspect provides a system for taking inter-clock correlation into account in on-chip timing derating. The system comprises a storage medium and an electronic design automation tool. The storage medium is configured to store data and clock path setup and hold early and late derate data. The electronic design automation tool is configured to employ at least some of said data and clock path setup and hold early and late derate data to calculate setup and hold slacks and total derate that take into account a correlation in delay variation between first and second clock paths as a function of depths thereof.
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