发明名称 |
Phase locked loop circuit with selectable feedback paths |
摘要 |
A phase locked loop (PLL) circuit is provided with selectable feedback paths. In one example, a method of operating a device includes passing a clock signal provided by a PLL circuit of the device through an internal feedback path of the PLL circuit to provide a first input signal to the PLL circuit while at least one external circuit of an external feedback path of the device is disabled during a low power operation mode of the device. The method also includes detecting a lock between the first input signal and a reference signal during the low power operation mode. The lock indicates that the clock signal is operating at a frequency used during a normal operation mode of the device. The method also includes passing the clock signal through the external feedback path to provide a second input signal to the PLL circuit. The method also includes switching from detecting a lock between the first input signal and the reference signal to detecting a lock between the second input signal and the reference signal if the external circuit is enabled for the normal operation mode.
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申请公布号 |
US8531222(B1) |
申请公布日期 |
2013.09.10 |
申请号 |
US201113079595 |
申请日期 |
2011.04.04 |
申请人 |
BRITTON BARRY;BOOTH RICHARD;JOHNSON PHILLIP L.;XU YANG;LI TAWEI DAVID;LATTICE SEMICONDUCTOR CORPORATION |
发明人 |
BRITTON BARRY;BOOTH RICHARD;JOHNSON PHILLIP L.;XU YANG;LI TAWEI DAVID |
分类号 |
H03L7/06 |
主分类号 |
H03L7/06 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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