Clock-edge modulated serial link with DC balance control
摘要
<p>A battery powered computing device has a channel configured as a single direct current balanced differential channel. A signal transmitter is connected to the channel. The signal transmitter is configured to apply clock edge modulated signals to the channel, where the clock edge modulated signals include direct current balancing control signals. A signal receiver is connected to the channel. The signal receiver is configured to recover the direct current balancing control signals.</p>
申请公布号
EP1780930(B1)
申请公布日期
2013.09.04
申请号
EP20060255352
申请日期
2006.10.18
申请人
SILICON IMAGE, INC.
发明人
KIM, GYUDONG;CHOE, WON JUN;JEONG, DEOG-KYOON;KIM, JAEHA;LEE, BONG-JOON;KIM, MIN-KYU