| 摘要 |
PROBLEM TO BE SOLVED: To provide a TEG manufacturing method and evaluation method which makes it possible to avoid the problem of junction leakage in a large-scale semiconductor integrated circuit device.SOLUTION: A plurality of first conductive type well regions ND electrically separately from each other are formed in a surface region 1S of a semiconductor substrate, and a second conductive type impurity region PW, a metal plug 8, and metal wiring M1 are connected to the surface region of each well region so as to compose a series current passage collectively. Then, if the well region ND concerned is a P-type well region (N-type well region), the potential of each well region is adjusted to a level which is substantially the lowest potential (highest potential) in the series current passage of that well region before wafer inspection is executed. |
