发明名称 DIGITAL PHASE LOCK LOOP AND METHOD THEREOF
摘要 An apparatus of digital phase lock loop and method are provided. In one embodiment, an apparatus comprises: an analog-to-digital converter (ADC) for converting a voltage level of an output clock into a first digital word in accordance with a timing defined by a reference clock; a first digital loop filter for receiving the first digital word and outputting a control code; a circuit to receive the reference clock and the output clock and output an offset code according to a frequency error of the output clock with respect to a frequency of the reference clock; an adder for generating an offset control code by summing the control code with the offset code; and a digitally controlled oscillator for outputting the output clock in accordance with the offset control code.
申请公布号 US2013222023(A1) 申请公布日期 2013.08.29
申请号 US201213405927 申请日期 2012.02.27
申请人 LIN CHIA-LIANG;REALTEK SEMICONDUCTOR CORP. 发明人 LIN CHIA-LIANG
分类号 H03L7/08 主分类号 H03L7/08
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