发明名称 SEMICONDUCTOR DEVICE HAVING HIERARCHICAL BIT LINE STRUCTURE
摘要 A semiconductor device comprises first and second global bit lines, a sense amplifier amplifying a voltage difference of the first and second global bit lines, first and second local bit lines corresponding to the first and second global bit lines, and first and second hierarchical switches controlling electrical connections between the first and second global bit lines and the first and second local bit line. In a precharge operation prior to accessing a selected memory cell belong to the first local bit lines, a pair of the first and second hierarchical switches, which is not in an access path, is kept ON, and remaining ones thereof are kept OFF. Subsequently, in an access to the selected memory cell, a first hierarchical switch of the pair is switched from ON to OFF, and simultaneously a first hierarchical switches in the access path is switched from OFF to ON.
申请公布号 US2013215698(A1) 申请公布日期 2013.08.22
申请号 US201313767481 申请日期 2013.02.14
申请人 ELPIDA MEMORY, INC.;ELPIDA MEMORY, INC. 发明人 NAGATA KYOICHI
分类号 G11C7/12;G11C7/08 主分类号 G11C7/12
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