| 摘要 |
PROBLEM TO BE SOLVED: To reduce a storage capacity of compressed data.SOLUTION: A logic circuit verification apparatus according to the prevent invention comprises a signal compressor that if for each cycle of a predetermined clock longer than that of a clock for actuating a logic circuit to be verified, finding one or more transitions of a signal to be verified for the logic circuit, outputs a first signal indicating that there is a transition of the signal to be verified, and if not finding any transition, outputs a second signal indicating that there is no transition of the signal to be verified. |
