发明名称 INTERCONNECTION STRUCTURE IN SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD FOR THE SAME
摘要 PURPOSE: A wire structure of a semiconductor device and a manufacturing method thereof are provided to suppress an RC delay by reducing parasitic capacitance between wires. CONSTITUTION: A first insulation layer (210) is formed on a semiconductor substrate (100). A wire mold layer (400) including a trench (411) is formed on the first insulation layer. A sidewall protection layer (511) including a silicide layer of a first metal is formed on the sidewall of the trench. A second metal wire (535) filling the trench is formed. A top protection layer (550) which protects the top surface of the second metal wire is formed.
申请公布号 KR20130092884(A) 申请公布日期 2013.08.21
申请号 KR20120014459 申请日期 2012.02.13
申请人 SK HYNIX INC. 发明人 RHO, IL CHEOL
分类号 H01L21/28 主分类号 H01L21/28
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