发明名称 Excess loop delay compensation for a continuous time sigma delta modulator
摘要 A method and corresponding apparatus are provided. In operation, an analog signal is integrated with an integrator to generate an integrated analog signal. The integrated analog signal is compared, in synchronization with a first clock signal and a second clock signal, to a reference voltage with a plurality of comparators to generate a comparator output signal. A feedback current is then generated, in synchronization with the second clock signal, from the comparator output signal. The feedback current is fed back to at least one of the comparators, and the comparator output signal is latched in synchronization with the first clock signal to generate a latched output signal. This latched output signal is converted to a feedback analog signal, and a difference between the analog signal and the feedback analog signal is determined.
申请公布号 US8514117(B2) 申请公布日期 2013.08.20
申请号 US201113229462 申请日期 2011.09.09
申请人 SRINIVASAN VENKATESH;SATARZADEH PATRICK;LIMETKAI VICTORIA W.;HAROUN BAHER;CORSI MARCO;TEXAS INSTRUMENTS INCORPORATED 发明人 SRINIVASAN VENKATESH;SATARZADEH PATRICK;LIMETKAI VICTORIA W.;HAROUN BAHER;CORSI MARCO
分类号 H03M3/00 主分类号 H03M3/00
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