| 摘要 |
A clock generation circuit includes, inter alia, a first phase detection block comparing initial phases of a reference clock signal and an output clock signal in response to an operation start signal, and outputting an initial phase difference detection signal corresponding to a comparison result; a second phase detection block comparing phases of the reference clock signal and the output clock signal, and outputting a phase detection signal corresponding to a comparison result; a variable unit delay block determined in a control range of the delay amount thereof in response to the initial phase difference detection signal, and delaying the reference clock signal by a delay amount corresponding to a voltage level of a control voltage and outputting the output clock signal; and a delay control block generating the control voltage which has the voltage level corresponding to the phase detection signal.
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