发明名称 COMPLEMENTARY MIS DEVICE MANUFACTURING METHOD
摘要 PROBLEM TO BE SOLVED: To provide a complementary MIS device in which sizes of a p-channel MOS transistor and an n-channel MOS transistor are balanced to each other.SOLUTION: The device includes a first gate electrode 33A formed on a principal plane of an Si substrate 31 via a first gate insulation film 32A at a first crystal orientation, and a second gate electrode 33B formed on the Si substrate via a second gate insulation film 32B at a second crystal orientation. The first gate electrode and the second gate electrode are commonly connected to each other, and the first gate insulation film and the second gate insulation film are formed on a face (110) or a face (111) of the Si substrate by plasma oxidization.
申请公布号 JP2013153176(A) 申请公布日期 2013.08.08
申请号 JP20130035741 申请日期 2013.02.26
申请人 TOHOKU UNIV;TOKYO ELECTRON LTD 发明人 OMI TADAHIRO;KOTANI KOJI;SUGAWA SHIGETOSHI
分类号 H01L21/8238;H01L21/316;H01L21/336;H01L27/092;H01L29/78 主分类号 H01L21/8238
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