发明名称 |
Reducing TAG-RAM accesses and accelerating cache operation during cache miss |
摘要 |
<p>This invention is a cache memory employing a tag bypass controller to detect a memory access to the same cache line as a last cache miss address and a last cache hit address. This information is uses for efficient data accesses and forwarding. Registers store the last miss-address and the last hit-address and corresponding valid flags. These hardware features allow reduced tag-RAM accesses and greatly reduce the latency required to fully re-stock a missed cache line. <IMAGE></p> |
申请公布号 |
EP1361518(B1) |
申请公布日期 |
2013.08.07 |
申请号 |
EP20030101290 |
申请日期 |
2003.05.09 |
申请人 |
TEXAS INSTRUMENTS INCORPORATED |
发明人 |
ZHANG, JONATHAN |
分类号 |
G06F12/08 |
主分类号 |
G06F12/08 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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