发明名称 Memory component having write operation with multiple time periods
摘要 A method for storing data in a memory chip that includes a memory core having dynamic random access memory cells, is performed by a memory controller chip. The method includes sending a write command to a first interface of the memory chip, wherein the write command specifies a write operation. After sending the write command, the memory controller chip waits for a first time period corresponding to a time period during which the write command is stored by the memory chip, and sends data associated with the write operation to a second interface of the memory chip, wherein the sending of the data occurs after a second time period transpires, the second time period following the first time period, such that sending the write command and sending the data are separated by a first predetermined delay time that includes both the first time period and the second time period.
申请公布号 US8504790(B2) 申请公布日期 2013.08.06
申请号 US201213424273 申请日期 2012.03.19
申请人 DAVIS PAUL G.;WARE FREDERICK A.;HAMPEL CRAIG E.;RAMBUS INC. 发明人 DAVIS PAUL G.;WARE FREDERICK A.;HAMPEL CRAIG E.
分类号 G06F12/00;G06F13/16 主分类号 G06F12/00
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