发明名称 HALL ELEMENT AND MANUFACTURING METHOD OF THE SAME
摘要 PROBLEM TO BE SOLVED: To provide a hall element capable of suppressing fluctuation of a depletion layer width depending on an input voltage without increasing consumption power and without affecting other mixedly mounted elements.SOLUTION: The hall element is formed which comprises: a first well layer 106 formed in a substrate 101 and injected with n-type impurities whose polarity is different from that of p-type impurities in the substrate 101; and a second well layer 107 formed outside of the first well layer 106 and injected with p-type impurities of the same polarity as that of the impurities in the first well layer 106 at a concentration lower than that in the first well layer 106.
申请公布号 JP2013149838(A) 申请公布日期 2013.08.01
申请号 JP20120010064 申请日期 2012.01.20
申请人 ASAHI KASEI ELECTRONICS CO LTD 发明人 GUNJI TOMOHIRO;KITAMURA TAKESHI
分类号 H01L43/06 主分类号 H01L43/06
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