发明名称 |
DUAL-CHANNEL ADC MINIMIZING INPUT SAMPLING-TIME MISMATCH |
摘要 |
PURPOSE: A dual channel analog to digital converter (ADC) is provided to sample an input signal by using a sampling clock of each channel by solving a mismatching problem. CONSTITUTION: An ADC comprises an SHA (110), an MDAC (120-130), an SHA sampling clock generator, and a flash ADC (140-160). An input end of the SHA or the MDAC constructs an X channel and a Y channel. The X channel shares an amplifier with the Y channel. The SHA sampling clock generator generates the sampling clock of the X channel and the sampling clock of the Y channel. The sampling clock of the X channel and the sampling clock of the Y channel are synchronized with a falling edge of a reference clock. A delay control circuit controls the delay time of a reference clock synchronizing with the SHA sampling clock generating the SHA sampling clock generator used in a digital correction circuit. |
申请公布号 |
KR20130084454(A) |
申请公布日期 |
2013.07.25 |
申请号 |
KR20120005253 |
申请日期 |
2012.01.17 |
申请人 |
SOGANG UNIVERSITY RESEARCH FOUNDATION |
发明人 |
LEE, SEUNG HOON;MYUNG, SUNG MEEN;KIM, HYO JIN |
分类号 |
H03M1/12 |
主分类号 |
H03M1/12 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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