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发明名称
于单一积体电路晶粒上使用不同闸氧化物厚度以实施多重积体电路之装置
摘要
本发明描述一种包含复数个功能积体电路区块之装置,每一功能积体电路区块系用不同氧化物厚度制造于一单体积体电路晶粒上。针对不同功能积体电路区块使用不同闸氧化物厚度提供经减少之功率消耗且增大处理系统中之效能。本发明呈现包含包括若干处理器核心及若干记忆体元件之若干功能积体电路区块之不同组合的若干实施例。
申请公布号
TWI402966
申请公布日期
2013.07.21
申请号
TW098116741
申请日期
2009.05.20
申请人
高通公司 美国
发明人
泰斯多里 罗诺J
分类号
H01L27/06
主分类号
H01L27/06
代理机构
代理人
陈长文 台北市松山区敦化北路201号7楼
主权项
地址
美国
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