发明名称 |
10T SRAM CELL WITH NEAR DUAL PORT FUNCTIONALITY |
摘要 |
An integrated circuit including an array of SRAM cells containing a write port with a write word line and two read buffers with read word lines. The write port includes passgate transistors connected to each data node of the SRAM cell. A process of operating the integrated circuit in which source nodes of read buffer driver transistors are biased during a read operation. A process of operating the integrated circuit in which source nodes of read buffer driver transistors are floated during a read operation. A process of operating the integrated circuit in which the write port and the read ports share data lines and the source nodes of read buffer driver transistors are floated during a write operation.
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申请公布号 |
US2013182492(A1) |
申请公布日期 |
2013.07.18 |
申请号 |
US201313783874 |
申请日期 |
2013.03.04 |
申请人 |
TEXAS INSTRUMENTS INCORPORATED;TEXAS INSTRUMENTS INCORPORATED |
发明人 |
HOUSTON THEODORE W. |
分类号 |
G11C11/419 |
主分类号 |
G11C11/419 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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