发明名称 GATE VOLTAGE CONTROLLED OSCILLATOR AND CLOCK DATA REGENERATION CIRCUIT
摘要 PROBLEM TO BE SOLVED: To provide a gate voltage controlled oscillator which can prevent unnecessary jitters without increasing a working current, and a clock data regeneration circuit.SOLUTION: In a gate voltage controlled oscillator, a gate signal is received and an oscillation signal having a frequency corresponding to the gate signal is output. The gate voltage controlled oscillator includes: a delay unit having a first and a second terminal, the delay unit delaying the oscillation signal received by the second terminal and outputting a delayed oscillation signal from the first terminal; and a multiplexer having a first and a second input terminal, a selection terminal, and an output terminal, with the first input terminal and the selection terminal supplied with the gate signal, the second input terminal connected to the first terminal of the delay unit, and the output terminal connected to the second terminal of the delay unit, the multiplexer receiving the delayed oscillation signal at the second input terminal, selecting a signal at the first or the second input terminal according to the gate signal, and outputting the selected signal as an oscillation signal from the output terminal.
申请公布号 JP2013141223(A) 申请公布日期 2013.07.18
申请号 JP20120278849 申请日期 2012.12.21
申请人 WELTRONICS COMPONENT LTD;TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD 发明人 YU BAI XIN;ZHANG JIA XIANG;WANG DING HAO
分类号 H04L7/02;H03L7/00 主分类号 H04L7/02
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