发明名称 Latency rate distortion optimisation
摘要 There is provided a method of improving latency in a Rate Distortion Optimization apparatus, comprising re-ordering processing of a sequence of 4×4 blocks of pixels received for processing by the Rate Distortion Optimization apparatus, the received order of the 4×4 blocks of pixels corresponding to the location of the 4×4 blocks of pixels within a macroblock, and processing the re-ordered sequence of 4×4 blocks in the Rate Distortion Optimization apparatus, where the re-ordering of the processing of the 4×4 blocks of pixels comprises interleaving the processing of two upper 4×4 blocks of pixels of a current 8×8 block with the processing of two lower 4×4 blocks of pixels of a previous 8×8 block. There is also provided a method of improving latency in a Rate Distortion Optimization apparatus, where the Rate Distortion Optimization apparatus assesses nine intra prediction modes and the method further comprises re-ordering processing of intra prediction modes such that a first six modes processed are not dependent on a block of pixels above and to the right of a current block of pixels, and processing the re-ordered sequence of intra prediction modes in the Rate Distortion Optimization apparatus.
申请公布号 US8488673(B2) 申请公布日期 2013.07.16
申请号 US20090555955 申请日期 2009.09.09
申请人 DENCHER ANTHONY PETER;TELEFONAKTIEBOLAGET LM ERICSSON (PUBL) 发明人 DENCHER ANTHONY PETER
分类号 H04B1/66;H04N7/12;H04N11/02;H04N11/04 主分类号 H04B1/66
代理机构 代理人
主权项
地址