| 摘要 |
An inverter delay compensation circuit includes a comparison determination unit including a first delay circuit configured for receiving a reference signal and having an inverter chain and a second delay circuit configured for receiving the reference signal and more insensitive to a PVT variation than the first delay circuit, and configured to compare delay amounts of signals obtained by passing the reference signal through the first and second delay circuits, respectively, and the comparison determination unit configured for generating a plurality of control signals; and a compensation circuit unit configured to compensate for a delay amount of an input signal in response to the plurality of control signals and configured to output an output signal.
|
