发明名称 MEMORY CONTROLLER, FLASH MEMORY SYSTEM, AND METHOD FOR CONTROLLING FLASH MEMORY
摘要 PROBLEM TO BE SOLVED: To reduce the number of bit errors of a flash memory.SOLUTION: When an error correction failure signal is input from a decoder (step S100), if a low-threshold data number Nw read from a flash memory 22 is less than a low-threshold data number Ni when the data is written in the flash memory 22, a memory controller executes a high bit line voltage application control (steps S120-S140) and, if the low-threshold data number Nw read from the flash memory 22 exceeds the low-threshold data number Ni when the data is written in the flash memory 22, repeatedly executes a readout On voltage application control (steps, S120, S130 and S150). This configuration can reduce the number of bit errors of the flash memory 22.
申请公布号 JP2013137848(A) 申请公布日期 2013.07.11
申请号 JP20110288679 申请日期 2011.12.28
申请人 UNIV OF TOKYO 发明人 TAKEUCHI TAKESHI;TANAKAMARU SHUHEI;YANAGIHARA YUKI
分类号 G11C16/02;G06F12/16;G11C16/06 主分类号 G11C16/02
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