SYNCHRONOUS SEQUENTIAL LOGIC DEVICE USING DOUBLE TRIGGERED FLIP-FLOPS AND METHOD FOR SKEWED TRIGGERING SUCH STATE STORING REGISTERS

摘要

Presented is an improved design or redesign concept for synchronous sequential logic devices using an alternative type of registers. Further a suitable clock-tree concept for such registers is proposed. 2.2. The special registers typically use a third additional latch to the traditional two master- and slave latches. This introduces latency between the overtaking and forwarding of information bits, between two edges of one or two clocks. These registers can be clocked with extreme clock skewing. 2.3. This new approach changes advantageously the time margins for setup and hold time between combinational connected registers. The extreme skewing reduces the peak currents. The concept allows also reducing the power dissipation. Existing netlist based designs may be quickly adapted to the new technology just by changing the involved register types and optimizing the clock tree.