发明名称 SAMPLE-AND-HOLD CIRCUIT ARRANGEMENT
摘要 Sample-and-hold circuits typically operate at maximum speed when the sampling phase is much shorter than the holding phase. Thus, a device driving the sampling capacitor is disconnected most of the time. Methods and apparatus use the holding phase to store the full charge required by the sampling capacitor to track the amplifier output in at least two "boost" capacitors configured such that when the sampling capacitor is switched to the driver, the boost capacitors are also switched to the driver. Thus, the sampling capacitor is almost instantly charged to the required voltage, and the driver needs to supply only any remaining "error" charge, avoiding delays due to driver output slewing.
申请公布号 WO2013093018(A1) 申请公布日期 2013.06.27
申请号 WO2012EP76680 申请日期 2012.12.21
申请人 ST-ERICSSON SA 发明人 MATEMAN, PAUL
分类号 G11C27/02 主分类号 G11C27/02
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