发明名称 |
SYSTEMS AND METHOD FOR UNBLOCKING A PIPELINE WITH SPONTANEOUS LOAD DEFERRAL AND CONVERSION TO PREFETCH |
摘要 |
Apparatuses, systems, and a method for providing a processor architecture with a control speculative load are described. In one embodiment, a computer-implemented method includes determining whether a speculative load instruction encounters a long latency condition, spontaneously deferring the speculative load instruction if the speculative load instruction encounters the long latency condition, and initiating a prefetch of a translation or of data that requires long latency access when the speculative load instruction encounters the long latency condition. The method further includes reaching a check instruction, which resteers to recovery code that executes a non-speculative version of the load. |
申请公布号 |
WO2013095392(A1) |
申请公布日期 |
2013.06.27 |
申请号 |
WO2011US66215 |
申请日期 |
2011.12.20 |
申请人 |
INTEL CORPORATION;MCCORMICK JR., JAMES, EARL |
发明人 |
MCCORMICK JR., JAMES, EARL |
分类号 |
G06F9/06;G06F9/30;G06F9/38;G06F12/10 |
主分类号 |
G06F9/06 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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