发明名称 |
Duty ratio correction circuit |
摘要 |
A duty ratio correction circuit for correcting a duty ratio of a clock signal. The duty ratio correction circuit includes an asymmetry buffer that receives a clock signal and adjusts a duty ratio of the clock signal in response to control signals; a clock generating circuit that is connected to the asymmetry buffer and detects the duty ratio of the clock signal; and a controller that generates the control signals according to the duty ratio of the clock signal. An operation of the controller is recorded as a program on a computer-readable recording medium.
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申请公布号 |
US8471616(B2) |
申请公布日期 |
2013.06.25 |
申请号 |
US201213533001 |
申请日期 |
2012.06.26 |
申请人 |
KIM YOUNG-WOOK;JANG SOON-BOK;SONG JONG-UK;OH HWA-SEOK;KIM SUNG-HA;SAMSUNG ELECTRONICS CO., LTD. |
发明人 |
KIM YOUNG-WOOK;JANG SOON-BOK;SONG JONG-UK;OH HWA-SEOK;KIM SUNG-HA |
分类号 |
H03L7/06 |
主分类号 |
H03L7/06 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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