发明名称 VERIFYING THE FUNCTIONALITY OF AN INTEGRATED CIRCUIT
摘要 Verifying the functionality of an integrated circuit, the integrated circuit being operable for processing a data packet thereby generating a data processing result. A data packet to be processed is evaluated to determine if the data packet is an erroneous data packet. If the data packet is identified as an erroneous data packet, a modified data packet is generated by modifying the erroneous data packet and providing the modified data packet to the integrated circuit. A determination is made as to whether the data processing result comprises the modification; and a malfunction of the integrated circuit is signaled, if the data processing result comprises the modification.
申请公布号 US2013142063(A1) 申请公布日期 2013.06.06
申请号 US201213685108 申请日期 2012.11.26
申请人 INTERNATIONAL BUSINESS MACHINES CORPORATION;INTERNATIONAL BUSINESS MACHINES CORPORATION 发明人 AMBALATH MATAYAMBATH ROOPESH;GREINER CARSTEN;JAYARAJ SENTHIL K.;RUF JUERGEN
分类号 H04L0012/000056 主分类号 H04L0012/000056
代理机构 代理人
主权项
地址