| 摘要 |
<P>PROBLEM TO BE SOLVED: To provide a multilayer wiring board for a semiconductor device, capable of suppressing stress concentration to a lead pin and void occurrence at bonding. <P>SOLUTION: A multilayer wiring board 100 for a semiconductor device is configured of conductive layers 104-109 and dielectric layers 111-117 in an alternately laminated manner, in which the uppermost surface and the lowest surface are formed of conductor layers 101, 102a, 102b and 109, and the conductor layers 101, 102a, 102b of the uppermost surface are formed of a bonding region 121 capable of contacting and bonding to lead pins 11, 12a, 12b included in the semiconductor device. The conductor layers 104-108 positioned beneath the bonding region 121 are formed of a plurality of isolated patterns orderly arranged in a two-dimensional array shape. <P>COPYRIGHT: (C)2013,JPO&INPIT |
